Daily's work of making embedded solutions (don't say IOT), is fiddling around with Ethernet interfacing.
Usually, you put a PHY chip or even a low-port count switch onto the board and connect this using RMII or RGMII to the microcontroller or FPGA. Then you usually do some low level interfacing and pass this to a higher level system like lwIP to build up the TCP/IP stack.
The typical tool for testing and debugging this is using Wireshark with your prototype connected to an Ethernet port of your PC.
But, did you know that before being shown on Wireshark, the data frame has to pass your PC's operating system first? And what if the packet is malformed or incomplete? Will be dropped. And how do you distinguish between your packets and those sent by the PC itself? You can't. What about the required gap between two frames?
Even more things to consider is when you do your own MAC on the FPGA. I did this. Several times and I know this can be a nightmare.
This is the motivation behind the Intona Ethernet Debugger.
A small device with two Gigabit Ethernet ports that acts like a cable, passes all data vice and versa. At the same time, it also passes all data to the USB 3.0 port right up to Wireshark on your PC (Linux, Mac, Windows). Shows really everything, including non-Ethernet frames (even the corrupt ones), time stamps, preambles, interpacket gaps and so on.
You can even make it actively disturb your data, being able to see how your system acts if data gets corrupted on the cable.
You want to see everything in Wireshark, don't you?
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